Updated
Updated · insights.trendforce.com · Aug 18
Intel Ramps EMIB-T for 2027 Volume Production as Yields Improve in AI Packaging Race
Updated
Updated · insights.trendforce.com · Aug 18

Intel Ramps EMIB-T for 2027 Volume Production as Yields Improve in AI Packaging Race

3 articles · Updated · insights.trendforce.com · Aug 18

Summary

  • Intel is pushing EMIB-T into high-volume production to support customer ramps in 2027, after what TrendForce described as a significant improvement in yields.
  • EMIB-T matters because chipmakers are breaking designs into chiplets as scaling costs rise toward 2nm and below, making dense, low-latency die-to-die interconnects a critical bottleneck.
  • Intel’s 2.5D approach embeds a silicon bridge in the substrate instead of using a full interposer, giving EMIB lower-cost potential than TSMC’s CoWoS if yield stability proves comparable.
  • TSMC said its 5.5x reticle CoWoS is already in volume production with yields above 98% and as high as 99%, underscoring the competitive pressure in AI-chip packaging.
  • Intel has said EMIB-T will scale beyond 8x reticle size this year and past 12x by 2028, though performance and reliability at larger scale still need broader validation.

Insights

Is advanced packaging—not transistor scaling—the real winner-takes-all battleground for AI chips as TSMC, Intel, and ASE race toward larger designs?
Will glass substrates and 3D/3.5D integration become the breakthrough that lowers AI package costs while enabling even bigger chiplet systems?
Can CoWoS, EMIB-T, and panel-level packaging scale fast enough to prevent packaging bottlenecks from slowing AI server growth?