Intel Expands U.S. AI Chip Packaging to 8x Reticle, Targets 12x by 2028
Updated
Updated · Intel · Jul 29
Intel Expands U.S. AI Chip Packaging to 8x Reticle, Targets 12x by 2028
2 articles · Updated · Intel · Jul 29
Summary
Intel said its Rio Rancho, New Mexico advanced-packaging operations now scale chip packages to 8x the industry reticle limit, with plans to exceed 12x by 2028 for AI semiconductors.
Foveros stacking and EMIB silicon bridges are the core technologies, letting Intel combine multiple chiplets into one high-performance package instead of relying on a single large chip.
EMIB-T, introduced in 2026, adds power-delivery channels through the bridge itself, improving efficiency and signal routing for high-bandwidth memory used in AI data-center chips.
The New Mexico site has grown from 25 employees in 1980 to 2,700 workers and 500 suppliers, which Intel says strengthens its U.S. foundry pitch as customers seek advanced packaging first.
That expansion follows another Intel packaging breakthrough reported later the same day: solving encapsulation for hyper-large chips, a step the company said could eventually enable 24x reticle-size packages.
As AI demands shatter traditional reticle limits, will Intel's void-free encapsulation breakthrough finally dethrone rivals in the advanced packaging race?
Can Intel's radical shift to glass substrates truly prevent severe warpage, or will brittleness shatter their panel-level packaging dreams?
With hyper-large chips hitting 25 kW, will liquid cooling innovations arrive in time to prevent these AI behemoths from melting down?