Quantum Digital Twin Cuts VLSI Energy 17% and Timing Error 22% for IoT Chips
Updated
Updated · Nature.com · Aug 17
Quantum Digital Twin Cuts VLSI Energy 17% and Timing Error 22% for IoT Chips
1 articles · Updated · Nature.com · Aug 17
Summary
A quantum-enhanced digital twin for low-power VLSI circuits improved dynamic power and timing optimization on standard benchmark chips, with energy consumption reduced by up to 17% and timing deviations cut by 22%.
The framework pairs classical telemetry and control with quantum routines: VQE minimizes energy states, QAOA identifies critical timing paths, and live IoT hardware data continuously updates the twin.
Tests on ISCAS-85 and ITC-99 circuits showed better power-estimation accuracy and critical-path prediction than classical simulation, while remaining robust under noise, process variation, and changing operating conditions.
The system uses selective quantum recalibration rather than continuous control, reflecting current hardware limits on qubits, coherence, and runtime but suggesting a practical path for adaptive IoT chip optimization.